A wide variety of memory devices are in common use. Commonly used memory devices include dynamic random access memory (“DRAM”) devices, static random access memory (“SRAM”) devices, flash memory devices, and programmable read only memory (“PROM”) devices, to name a few. All of these memory devices have certain properties in common. For example, the capacity and operating speed of such memory devices have continuously increased with time. Also, these memory devices utilize a large number of memory cells that are arranged in arrays or banks containing rows and columns.
Each bank of memory cells can be thought of as a memory device “building block” so that the capacity of a memory device can be increased simply by increasing the number of banks in the memory device. For example, as illustrated in FIG. 1, an architecture for a memory device 10 includes a plurality of data terminals 12a-z for coupling write data to and read data from the memory device 10. The data terminals 12 typically number in powers of 2, with 8, 16 and 32 data terminals currently being common. Each data terminals 12 is selectively coupled to memory cells in the memory device 10. The memory device 10 contains 8 banks 20-34 of memory cells fabricated in an array area of a silicon substrate, with each bank being divided into two sections a,b by a respective midgap region 40. The memory cells in the low-order banks 20-26 are selectively coupled through a first plurality of common local data read/write (“LDRW”) lines 50 to a first set of respective data terminals 12 on the left side of the memory device 10 as shown in FIG. 1. However, only a single LDRW line 50 connected to a single data terminal 12 on the left side is shown in FIG. 1 for purposes of clarity, it being understood that each data terminal 12 is connected to a respective LDRW line 50. Similarly, the memory cells in the high-order banks 28-34 are selectively coupled through a second plurality of LDRW lines 54 to a second set of respective data terminals 12 on the right-hand side of the memory device 10, although only one such line 54 is shown for purposes of clarity.
As shown in FIG. 1, the LDRW lines 50, 54 are connected to the respective data terminals 12 through respective terminal data drivers 60, 64, which may be of conventional or subsequently developed design. The terminal data drivers 60, 64 couple write data from the data terminals 12 to the respective LDRW lines 50, 54, and couple read data from the LDRW lines 50, 54 to the respective data terminals 12. Each bank 20-34 of memory cells also includes a respective array data driver (“ADD”) circuit 70 that is fabricated in the midgap region 40 of the respective bank. The ADDs 70 may be conventional or subsequently developed circuitry. As is well known in the art, each of the ADDs 70 couple write data from the respective LDRW line 50, 54 to a respective input/output (“I/O”) line (not shown), and couple read data from a differential sense amplifier (not shown) to the respective LDRW line 50, 54. As is well known in the art, the differential sense amplifier receives the read data from the respective I/O line.
As mentioned above, the capacity of memory devices can be increased simply by including a larger number of banks of memory cells. However, as the number of banks is increased, the lengths of the LDRW lines 50, 54 must be correspondingly increased as well. Unfortunately, the capacitance and resistance of the LDRW lines 50, 54 also increases with length, thus increasing the time required to couple data to and from memory cells in the banks, particularly those banks 26, 34 that are farther from the data terminals 12. As mentioned above, the operating speed of memory devices has also increased with time. Thus, the trend of increasing capacity is, to some extent, inconsistent with the trend toward higher operating speeds. For this reason, unless the problem of increased LDRW line capacitance and resistance can be solved, it may be necessary to trade off memory capacity for operating speed.
The problem of increased LDRW line capacitance and resistance potentially limiting memory device operating speed is also encountered in coupling data signals through data lines other than LDRW lines or other signal lines in memory arrays. For example, it is common for data lines known as bit lines or digit lines to extend through a memory array for coupling individual memory cells in the respective column of the array to a respective sense amplifier. The digit lines are, in turn, selectively coupled to the I/O lines. As the size of arrays continues to increase to provide increased memory capacity, the lengths of these digit lines are also increased, thus increasing their capacitance and resistance, which also tends to slow the operating speed of memory devices. Similar problems are encountered in coupling signals through other signal lines in an array, such as word lines.
There is therefore a need for devices and methods for more quickly coupling data signals through data lines such as LDRW lines and through other signal lines in memory arrays so that the capacity of memory devices can be increased without limiting operating speed.